The present invention relates to a level converter circuit converting an ECL (Emitter-Coupled Logic)--level signal to a TTL (Transistor-Transistor Logic)--level signal, and more particularly, to a level converter circuit having a three-state TTL output level.
Circuits have heretofore been represented by ECL and CML for forming high-speed logic circuits. In particular, ECL has been placed in the market having various functions as represented by standard SSI devices. In recent years, LSI's and semi-custom master slices constituted by ECL have been put into the market. To utilize their high-speed performance, these devices usually employ an ECL interface in the input/output portion. The ECL interface is very effective and makes it possible to constitute the highest system when the system to be constituted all has the ECL logic level, using neither TTL nor CMOS devices of dissimilar logic levels. Such a case, however, is limited to the periphery of a main frame of a large computer. In the general logic devices, a plurality of interface levels have been required accompanying the introduction of the newest microcomputer control or the semiconductor memory. That is, the high-speed operation portion of the device is constituted by ECL, but the control portion thereof is controlled by a microcomputer which is a standard device, and the memory portion is constituted by a cheaply constructed semiconductor memory device which also is a standard device. At present, these standard products are designed to meet input/output interface of the most general TTL or CMOS level. Even in the portion designed with ECL, therefore, as the integrated degree thereof increases, it becomes difficult to obtain the logic in a form in which the interface level is completely separated. Even in a single ECL device, therefore, some input/output terminals must input or output the signals on the TTL or CMOS level. In the conventional means which employs the interface, provision is made of a level converter IC as a standard product for converting the TTL level into the ECL level or for converting the ECL level into the TTL level as shown, for example, in "MECL INTEGRATED CIRCUITS DATA BOOK" No. 3, September, 1973, MOTOROLA Inc. 3-56.
A level converter can convert an ECL-level input having two-state (ECL High level state and ECL Low level state) to a TTL-level output having three-state (TTL High level state, TTL Low level state and floating state). The level converter having a three-state TTL output level can be constructed by adding circuit elements to a level converter having a two-state TTL output level (TTL High level state and TTL Low Level state) for forming the floating output state. On the other hand, the output terminal of the level converter of three-state TTL output is often connected to a bus line and may, hence, be connected to TTL output terminals of other IC's. In this case, the level converter must be so designed that when the applying negative power source is delayed behind the positive power source or when the negative power source is interrupted, the output terminal thereof exhibits a high impedance, that is, a floating condition to protect the other IC's connected to the output terminal of the level converter from the damage. Therefore, a protecting circuit is necessary in the level converter. That is, in a prior art level converter having three-state TTL output, both circuits, one is for forming a floating state of the output terminal in accordance with an ECL input signal, and the other is for forming a floating condition of the output terminal against the abnormal power supply conditions, are necessary. Therefore, the level converter having three-state TTL output in the prior art necessitates many circuit elements thereby causing the chip size to increase, obstructing a high integration of the device and impairing a high-speed operation by unfavorable junction capacitances of the circuit elements.